Rainbow Electronics W90N740 - Manual (Page 131)

W90N740
Publication Release Date: November 26, 2004
- 127 - Revision A4
7.7 GDMA Controller
The GDMA Controller of W90N740 is a two-channel general DMA controller. The two-channel GDMA
performs the following data transfers without the CPU intervention:
• Memory-to-memory (memory to/from memory)
• Memory –to – IO
• IO- to -memory
The GDMA can be started by the software or external DMA request nXDREQ1/2/3. Software can also be
used to restart the GDMA operation after it has been stopped. The CPU can recognize the completion of
a GDMA operation by software polling or when it receives an internal GDMA interrupt. The W90N740
GDMA controller can increase source or destination address, decrease them as well, and conduct 8-bit
(byte), 16-bit (half-word), or 32-bit (word) data transfers.
The Features of the GDMA ：
• 2 Channel GDMA for memory-to-memory data transfers without CPU intervention
• Increase or decrease source / destination address in 8-bit, 16-bit, or 32-bit data transfers
• Supports 4-data burst mode to boost performance
• Support external GDMA request by through bank 3
7.7.1 GDMA Function Description
The GDMA directly transfers data between source and destination. The GDMA starts to transfer data
after it receives service requests from nXDREQ1/2/3 signal or software. When the entire data have been
transferred completely, the GDMA becomes idle. Nevertheless, if another transfer is needed, then the
GDMA must be programmed again.
There are three transfer modes:
• Single Mode
Single mode requires a GDMA request for each data transfer. A GDMA request (nXDREQ1/2/3 or
software) causes one byte, one half-word, or one word to transfer if the 4-data burst mode is
disabled, or four times of transfer width is the 4-data burst mode is enabled.
• Block Mode
The assertion of a single GDMA request causes all of the data to be transferred in a single
operation. The GDMA transfer is completed when the current transfer count register reaches zero.
• Demand Mode
The GDMA continues transferring data until the GDMA request input nXDREQ1/2/3 becomes
inactive.