Rainbow Electronics W90N740 User Manual
Page 3
W90N740
Publication Release Date: November 26, 2004
- III -
Revision A4
Table of Contents-
1.
GENERAL DESCRIPTION .......................................................................................................... 1
2.
FEATURES .................................................................................................................................. 1
3.
BLOCK DIAGRAM ....................................................................................................................... 5
4.
PIN CONFIGURATION ................................................................................................................ 6
5.
PIN ASSIGNMENT ...................................................................................................................... 7
6.
PIN DESCRIPTION.................................................................................................................... 10
7.
FUNCTIONAL DESCRIPTION .................................................................................................. 14
7.1
ARM7TDMI CPU Core................................................................................................. 14
7.2
System Manager.......................................................................................................... 15
7.2.1
Overview .......................................................................................................................15
7.2.2
System Memory Map.....................................................................................................15
7.2.3
Address Bus Generation ...............................................................................................17
7.2.4
Data Bus Connection with External Memory .................................................................18
7.2.5
Bus Arbitration...............................................................................................................27
7.2.6
Power-On Setting ..........................................................................................................28
7.2.7
System Manager Control Registers Map.......................................................................29
7.3
External Bus Interface (EBI) ........................................................................................ 35
7.3.1
EBI Overview.................................................................................................................35
7.3.2
SDRAM Controller.........................................................................................................35
7.3.3
External Bus Mastership................................................................................................41
7.3.4
EBI Control Registers Map ............................................................................................41
7.4
Cache Controller.......................................................................................................... 59
7.4.1
On-Chip RAM ................................................................................................................59
7.4.2
Non-Cacheable Area .....................................................................................................59
7.4.3
Instruction Cache ..........................................................................................................59
7.4.4
Data Cache ...................................................................................................................62
7.4.5
Write Buffer ...................................................................................................................64
7.5
Ethernet MAC Controller (EMC) .................................................................................. 68
7.5.1
EMC Descriptors ...........................................................................................................68
7.5.2
7.5.2 EMC Register Mapping ........................................................................................73
7.6
Network Address Translation Accelerator (NATA).................................................... 114
7.6.1
NAT Process Flow.......................................................................................................115
7.6.2
NATA Registers Map...................................................................................................116
7.7
GDMA Controller ....................................................................................................... 127
7.7.1
GDMA Function Description ........................................................................................127
7.7.2
GDMA Registers Map .................................................................................................128