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Bit error – EXFO FTB/IQS-88000 Series Power Blazer for FTB-2/2Pro/500/IQS-600 User Manual

Page 117

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Test Setup - Test Configurator, Timer, and System

Power Blazer

105

BERT and Unframed BERT

All Lanes check box is available with an unframed test with parallel
interface. When selected, it allows to set the same TX and/or RX test
pattern for all lanes. When All Lanes check box is cleared (default), a
different test pattern may be set for each lane.

When the All Lanes check box is cleared, for an unframed test, the
following pattern settings are available for each lane.

TX Pattern/RX Pattern: Select the test pattern from the list for each
lane and direction (TX and RX). Choices are PRBS9, PRBS11, PRBS15,
PRBS20, PRBS23, and PRBS31 (default).

Invert check box, when selected (cleared by default), inverts the test
pattern meaning that every 0 will be changed for 1 and every 1 for 0.
For example, the pattern 1100 will be sent as 0011.

Pattern Sync icon indicates the status of the received signal pattern.
Refer to Status Bar on page 24 for more information.

Bit Error

Pass/Fail Verdict allows to enable bit-error-rate pass/fail verdict by
selecting either Bit Error Count or Bit Error Rate. The default value is
Disabled.

BER Threshold allows to enter the threshold Count or Rate value that
will be used to declare the pass/fail verdict. The BER Threshold
applies to individual pattern for Multi-Pattern.

For Count, enter the maximum bit error count allowed before
declaring a fail verdict: 0 (default) to 999999.

For Rate, enter the maximum bit error rate allowed before declaring a
fail verdict: 1.0E-14 to 1.9E-01. The default value is 1.0E-12.