NEC PD78F9488 - Manual (Page 337)

CHAPTER 21 INSTRUCTION SET
User’s Manual U15331EJ4V1UD
337
Mnemonic Operands Bytes Clocks Operation Flag
Z AC CY
CMP A, #byte 2 4 A − byte x x x
saddr, #byte 3 6 (saddr) − byte x x x
A, r 2 4 A − r x x x
A, saddr 2 4 A − (saddr) x x x
A, !addr16 3 8 A − (addr16) x x x
A, [HL] 1 6 A − (HL) x x x
A, [HL+byte] 2 6 A − (HL + byte) x x x
ADDW AX, #word 3 6 AX, CY ← AX + word x x x
SUBW AX, #word 3 6 AX, CY ← AX − word x x x
CMPW AX, #word 3 6 AX − word x x x
INC r 2 4 r ← r + 1 x x
saddr 2 4 (saddr) ← (saddr) + 1 x x
DEC r 2 4 r ← r − 1 x x
saddr 2 4 (saddr) ← (saddr) − 1 x x
INCW rp 1 4 rp ← rp + 1
DECW rp 1 4 rp ← rp − 1
ROR A, 1 1 2 (CY, A
7
← A
0
, A
m −1
← A
m
) × 1 x
ROL A, 1 1 2 (CY, A
0
← A
7
, A
m+1
← A
m
) × 1 x
RORC A, 1 1 2 (CY ← A
0
, A
7
← CY, A
m −1
← A
m
) × 1 x
ROLC A, 1 1 2 (CY ← A
7
, A
0
← CY, A
m+1
← A
m
) × 1 x
SET1 saddr.bit 3 6 (saddr.bit) ← 1
sfr.bit 3 6 sfr.bit ← 1
A.bit 2 4 A.bit ← 1
PSW.bit 3 6 PSW.bit ← 1 x x x
[HL].bit 2 10 (HL).bit ← 1
CLR1 saddr.bit 3 6 (saddr.bit) ← 0
sfr.bit 3 6 sfr.bit ← 0
A.bit 2 4 A.bit ← 0
PSW.bit 3 6 PSW.bit ← 0 x x x
[HL].bit 2 10 (HL).bit ← 0
SET1 CY 1 2 CY ← 1 1
CLR1 CY 1 2 CY ← 0 0
NOT1 CY 1 2 CY ← CY x
Remark One instruction clock cycle is one CPU clock cycle (f
CPU
) selected by the processor clock control
register (PCC).