NEC PD78F9488 - Manual (Page 160)

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61
User’s Manual U15331EJ4V1UD
160
7.5 Cautions on Using 8-Bit Timers 50, 60, and 61
(1) Error on starting timer
An error of up to 1.5 clocks is included in the time between the timer being started and a match signal being
generated. This is because the rising edge is detected and the counter is incremented if the timer is started
while the count clock is high (see Figure 7-31).
Figure 7-31. Case in Which Error of 1.5 Clocks (Max.) Occurs
8-bit timer counter n0
(TMn0)
Count
pulse
Clear signal
Selected clock
TCEn0
Delay A
Delay B
Selected clock
TCEn0
Clear signal
Count pulse
TMn0 counter value 00H 01H 02H 03H
Delay A
Delay B
An error of up to 1.5 clocks occurs if the timer is started
when the selected clock is high and delay A > delay B.
Remark nm = 50, 60, 61
(2) Setting of 8-bit compare register nm
8-bit compare register nm (CRnm) can be set to 00H.
Therefore, one pulse can be counted when the 8-bit timer operates as an event counter.
Remark nm= 50, 60, 61
Figure 7-32. Timing of Operation as External Event Counter (8-Bit Resolution)
TMI60 input
CR60 00H
TM60
count value
00H 00H 00H 00H
Interrupt request flag