NEC PD78F9488 - Manual (Page 335)

CHAPTER 21 INSTRUCTION SET
User’s Manual U15331EJ4V1UD
335
Mnemonic Operands Bytes Clocks Operation Flag
Z AC CY
MOVW rp, #word 3 6 rp ← word
AX, saddrp 2 6 AX ← (saddrp)
saddrp, AX 2 8 (saddrp) ← AX
AX, rp Note 1 4 AX ← rp
rp, AX Note 1 4 rp ← AX
XCHW AX, rp Note 1 8 AX ↔ rp
ADD A, #byte 2 4 A, CY ← A + byte x x x
saddr, #byte 3 6 (saddr), CY ← (saddr) + byte x x x
A, r 2 4 A, CY ← A + r x x x
A, saddr 2 4 A, CY ← A + (saddr) x x x
A, !addr16 3 8 A, CY ← A + (addr16) x x x
A, [HL] 1 6 A, CY ← A + (HL) x x x
A, [HL+byte] 2 6 A, CY ← A + (HL + byte) x x x
ADDC A, #byte 2 4 A, CY ← A + byte + CY x x x
saddr, #byte 3 6 (saddr), CY ← (saddr) + byte + CY x x x
A, r 2 4 A, CY ← A + r + CY x x x
A, saddr 2 4 A, CY ← A + (saddr) + CY x x x
A, !addr16 3 8 A, CY ← A + (addr16) + CY x x x
A, [HL] 1 6 A, CY ← A + (HL) + CY x x x
A, [HL+byte] 2 6 A, CY ← A + (HL + byte) + CY x x x
SUB A, #byte 2 4 A, CY ← A − byte x x x
saddr, #byte 3 6 (saddr), CY ← (saddr) − byte x x x
A, r 2 4 A, CY ← A − r x x x
A, saddr 2 4 A, CY ← A − (saddr) x x x
A, !addr16 3 8 A, CY ← A − (addr16) x x x
A, [HL] 1 6 A, CY ← A − (HL) x x x
A, [HL+byte] 2 6 A, CY ← A − (HL + byte) x x x
Note Only when rp = BC, DE, or HL.
Remark One instruction clock cycle is one CPU clock cycle (f
CPU
) selected by the processor clock control
register (PCC).