NEC PD78F9488 - Manual (Page 273)

CHAPTER 15 REMOTE CONTROLLER RECEIVER ( µ PD789489, 78F9489 ONLY)
User’s Manual U15331EJ4V1UD
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(2) Remote controller receive data register (RMDR)
This register holds the remote controller reception data. When the remote controller receive shift register
(RMSR) overflows, the data in RMSR is transferred to RMDR. Bit 7 stores the last data, and bit 0 stores the
first data. INTDFULL is generated at the same time as data is transferred from RMSR to RMDR.
RMDR is read with an 8-bit memory manipulation instruction.
RESET input sets RMDR to 00H.
When the remote controller operation is disabled (RMEN
= 0), RMDR is cleared to 00H.
Caution When INTDFULL has been generated, read RMDR before the next 8-bit data is received. If the
next INTDFULL is generated before the read operation is complete, RMDR is overwritten.
(3) Remote controller shift register receive counter register (RMSCR)
This is an 8-bit counter register used to indicate the number of valid bits remaining in the remote controller
receive shift register (RMSR) when remote controller reception is complete (INTREND is generated). Reading
the values of this register allows confirmation of the number of bits, even if the received data is in a format
other than an integral multiple of 8 bits.
RMSCR is read with an 8-bit memory manipulation instruction.
RESET input sets RMSCR to 00H.
It is cleared to 00H under any of the following conditions.
• Remote controller stops operation (RMEN = 0).
• Error is detected (INTRERR is generated).
• RMSR is read after INTREND has been generated.
Caution When INTREND has been generated, immediately read RMSCR before reading RMSR. If
reading occurs at another timing, the value is not guaranteed.
Figure 15-2. Operation Examples of RMSR, RMSCR, and RMDR Registers
When Receiving 1010101011111111B (16 Bits)
RMSR
7 6 5 4 3 2 1 0
RMSCR RMDR
After reset 0 0 0 0 0 0 0 0 00H 00000000B
Receiving 1 bit 1 0 0 0 0 0 0 0 01H 00000000B
Receiving 2 bits 0 1 0 0 0 0 0 0 02H 00000000B
Receiving 3 bits 1 0 1 0 0 0 0 0 03H 00000000B
… … … … … … … … … … …
Receiving 7 bits 1 0 1 0 1 0 1 0 07H 00000000B
Receiving 8 bits
↓
RMDR transfer
0
↓
0 1
↓
0 0
↓
0 1
↓
0 0
↓
0 1
↓
0 0
↓
0 1
↓
0 00H
↓
00H
00000000B
↓
01010101B
Receiving 9 bits 1 0 0 0 0 0 0 0 01H 01010101B
Receiving 10 bits 1 1 0 0 0 0 0 0 02H 01010101B
… … … … … … … … … … …
Receiving 16 bits
↓
RMDR transfer
1
↓
0 1
↓
0 1
↓
0 1
↓
0 1
↓
0 1
↓
0 1
↓
0 1
↓
0 00H
↓
00H
01010101B
↓
11111111B