NEC PD78F9488 User Manual
Page 188
CHA
PTER 11 SERIA
L INTERFA
C
E 20
188
User’s Manual U15331EJ4V1UD
Clock for receive detection
Transmit shift clock
Receive shift clock
Receive detection
TXE20
RXE20
CSIE20
1/2
1/2
Transmit clock
counter (3 bits)
Receive clock
counter (3 bits)
4
f
X
/2
f
X
/2
3
f
X
/2
4
f
X
/2
5
f
X
/2
6
f
X
/2
7
f
X
/2
8
f
X
/2
2
ASCK20/SCK20/P20
TPS203 TPS202 TPS201 TPS200
Baud rate generator control
register 20 (BRGC20)
Internal bus
Selector
Selector
Selector
Figure 11-2. Block Diagram of Baud Rate Generator 20