NEC PD78F9488 - Manual (Page 187)

CHA
PTER 11 SERIA
L INTERFA
C
E 20
User’s Manual U15331EJ4V1UD
187
Internal bus
Receive buffer
register 20 (RXB20)
Switch of the first bit
Asynchronous serial interface
status register 20 (ASIS20) Serial operation mode
register 20 (CSIM20)
Receive shift register
20 (RXS20)
CSIE20 DIR20 CSCK20 PE20 FE20 OVE20 TXE20 RXE20 PS201 PS200 CL20 SL20
Asynchronous serial interface
mode register 20 (ASIM20)
Transmit shift register
20 (TXS20) Transmit shift
clock
Selector CSIE20
Data phase
control
Receive shift
clock
SI20/P22
/RxD20
SO20/P21
/TxD20
4
Parity detection
Detection of stop bit
Receive data counter
Parity operation
Addition of stop bit
Transmit data counter
SL20, CL20, PS200, PS201
Reception enable
Receive clock
Detection clock
Detection
of start bit
Port mode
register (PM20)
CSIE20
CSCK20
SCK20/P20
/ASCK20
Receive
detection
Internal clock
output
External clock input
Transmit/receive
clock control
Baud rate
generator Note
4
TPS203 TPS202 TPS201 TPS200
CSIE20
CSCK20
f X /2 to f X /2 8
Baud rate generator control
register 20 (BRGC20)
INTST20
INTSR20/INTCSI20
Internal bus
Port mode
register (PM21)
Clock phase
control
Output latch
(P21)
Output latch
(P20)
Figure 11-1. Block Diagram of Serial Interface 20
Note See Figure11-2 for the configuration of the baud rate generator.