NEC PD78F9488 - Manual (Page 118)

CHAPTER 6 16-BIT TIMER 20
118
User’s Manual U15331EJ4V1UD
6.5 Cautions on Using 16-Bit Timer 20
6.5.1 Restrictions when rewriting 16-bit compare register 20
(1) Disable interrupts (TMMK20 = 1) and inversion control of timer output (TOC20 = 0) before rewriting the
compare register (CR20).
If the value in CR20 is rewritten in the interrupt-enabled state, an interrupt request may occur at the moment
of rewrite.
(2) Depending on the timing of rewriting the compare register (CR20), the interval time may become twice as
long as the intended time. Similarly, a shorter waveform or twice-longer waveform than the intended timer
output waveform may be output.
To avoid this problem, rewrite the compare register using either of the following procedures.
When rewriting using 8-bit access
<1> Disable interrupts (TMMK20 = 1) and inversion control of timer output (TOC20 = 0).
<2> First rewrite the higher byte of CR20 (16 bits).
<3> Then rewrite the lower byte of CR20 (16 bits).
<4> Clear the interrupt request flag (TMIF20).
<5> Enable timer interrupts/timer output inversion after half a cycle or more of the count clock has elapsed from
the start of the interrupt.
(count clock = 32/f
X
, CPU clock = f
X
)
TM20_VCT: SET1 TMMK20 ; Disable timer interrupts (6 clocks)
CLR1 TMC20.3
; Disable timer output inversion (6 clocks)
MOV A, #xxH
; Set the rewrite value of the higher byte (6 clocks)
MOV !0FF17H, A
; Rewrite the CR20 higher byte (8 clocks)
MOV A, #yyH
; Set the rewrite value of the lower byte (6 clocks)
MOV !0FF16H,A
; Rewrite the CR20 lower byte (8 clocks)
CLR1 TMIF20
; Clear the interrupt request flag (6 clocks)
CLR1 TMMK20
; Enable timer interrupts (6 clocks)
SET1 TMC20.3
; Enable timer output inversion
Note Because the INTTM20 signal becomes high level for half a cycle of the count clock after an interrupt is
generated, the output is inverted if TOC20 is set to 1 during this period.
Total: 16 clocks
or more
Note