NEC PD78F9488 - Manual (Page 171)

CHAPTER 9 WATCHDOG TIMER
User’s Manual U15331EJ4V1UD
171
9.4 Watchdog Timer Operation
9.4.1 Operation as watchdog timer
The watchdog timer detects a program loop when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is
set to 1.
The count clock (program loop detection time interval) of the watchdog timer can be selected by bits 0 to 2
(WDCS0 to WDCS2) of watchdog timer clock selection register (WDCS). By setting bit 7 (RUN) of WDTM to 1, the
watchdog timer is started. Set RUN to 1 within the set program loop detection time interval after the watchdog timer
has been started. By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1,
and the program loop detection time is exceeded, a system reset signal or a non-maskable interrupt is generated,
depending on the value of bit 3 (WDTM3) of WDTM.
The watchdog timer continues operation in HALT mode, but stops in STOP mode. Therefore, first set RUN to 1 to
clear the watchdog timer before executing the STOP instruction.
Cautions 1. The actual program loop detection time may be up to 0.8% shorter than the set time.
2. When the subsystem clock is selected as the CPU clock, the watchdog timer count
operation is stopped. Even when the main system clock continues oscillating in this case,
watchdog timer count operation is stopped.
Table 9-4. Watchdog Timer Program Loop Detection Time
WDCS2 WDCS1 WDCS0 Program Loop Detection Time At f
X
= 5.0 MHz
0 0 0 2 11 × 1/f
X
410 µ s
0 1 0 2 13 × 1/f
X
1.64 ms
1 0 0 2 15 × 1/f
X
6.55 ms
1 1 0 2 17 × 1/f
X
26.2 ms
f
X
: Main system clock oscillation frequency