NEC PD78F9488 User Manual
Page 255
CHAPTER 13 LCD CONTROLLER/DRIVER
User’s Manual U15331EJ4V1UD
255
(2) LCD clock control register 0 (LCDC0)
LCDC0 specifies the LCD source clock and LCD clock. The frame frequency is determined according to the
LCD clock and number of time slices.
LCDC0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets LCDC0 to 00H.
Figure 13-4. Format of LCD Clock Control Register 0
LCDC03 LCDC02 LCDC01 LCDC00
LCDC0
Symbol
Address
After reset
R/W
FFB2H
00H
R/W
7
6
5
4
3
2
1
0
LCD source clock (f
LCD
) selection
Note
LCDC03
0
0
1
1
LCDC02
0
1
0
1
LCD clock (LCDCL) selection
LCDC01
0
0
1
1
LCDC00
0
1
0
1
0
0
0
0
f
LCD
/2
6
f
LCD
/2
7
f
LCD
/2
8
f
LCD
/2
9
f
XT
(32.768 kHz)
f
X
/2
5
(156.3 kHz)
f
X
/2
6
(78.1 kHz)
f
X
/2
7
(39.1 kHz)
Note Specify an LCD source clock (f
LCD
) frequency of at least 32 kHz.
Cautions 1. Bits 4 to 7 must be set to 0.
2. Before changing the LCDC0 setting, be sure to stop voltage boosting (VAON0 = 0).
3. Set the frame frequency to 128 Hz or lower.
Remarks 1. f
X
: Main system clock oscillation frequency
2. f
XT
: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at f
X
= 5.0 MHz or f
XT
= 32.768 kHz.
As an example, Table 13-3 lists the frame frequencies used when f
XT
(32.768 kHz) is supplied as the LCD
source clock (f
LCD
).
Table 13-3. Frame Frequencies (Hz)
LCD Clock (LCDCL)
Time Slots
f
XT
/2
9
(64 Hz)
f
XT
/2
8
(128 Hz)
f
XT
/2
7
(256 Hz)
f
XT
/2
6
(512 Hz)
3
21
43
85
171
Note
4
16
32
64
128
Note This setting is prohibited because it causes the frame frequency to exceed 128 Hz.