NEC PD78F9488 - Manual (Page 11)

User’s Manual U15331EJ4V1UD
11
CONTENTS
CHAPTER 1 GENERAL ..........................................................................................................................26
1.1 Features ......................................................................................................................................26
1.2 Applications ...............................................................................................................................26
1.3 Ordering Information .................................................................................................................27
1.4 Pin Configuration (Top View) ...................................................................................................28
1.5 78K/0S Series Lineup ................................................................................................................31
1.6 Block Diagram............................................................................................................................34
1.7 Overview of Functions ..............................................................................................................35
CHAPTER 2 PIN FUNCTIONS...............................................................................................................37
2.1 List of Pin Functions .................................................................................................................37
2.2 Description of Pin Functions....................................................................................................40
2.2.1 P00 to P07 (Port 0) ....................................................................................................................... 40
2.2.2 P10, P11 (Port 1) .......................................................................................................................... 40
2.2.3 P20 to P25 (Port 2) ....................................................................................................................... 40
2.2.4 P30 to P34 (Port 3) ....................................................................................................................... 41
2.2.5 P50 to P53 (Port 5) ....................................................................................................................... 41
2.2.6 P60 to P67 (Port 6) ....................................................................................................................... 42
2.2.7 P70 to P73 (Port 7) ....................................................................................................................... 42
2.2.8 P80 to P87 (Port 8) ....................................................................................................................... 42
2.2.9 S0 to S27 ...................................................................................................................................... 42
2.2.10 COM0 to COM3 ............................................................................................................................ 42
2.2.11 V
LC0
to V
LC2
................................................................................................................................... 42
2.2.12 CAPH, CAPL................................................................................................................................. 42
2.2.13 RESET.......................................................................................................................................... 43
2.2.14 X1, X2 ........................................................................................................................................... 43
2.2.15 XT1, XT2....................................................................................................................................... 43
2.2.16 AV
DD
.............................................................................................................................................. 43
2.2.17 AV
SS
.............................................................................................................................................. 43
2.2.18 V
DD
................................................................................................................................................ 43
2.2.19 V
SS
................................................................................................................................................ 43
2.2.20 V
PP
(flash memory version only).................................................................................................... 43
2.2.21 IC0 (mask ROM version only) ....................................................................................................... 44
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ........................................45
CHAPTER 3 CPU ARCHITECTURE......................................................................................................48
3.1 Memory Space............................................................................................................................48
3.1.1 Internal program memory space ................................................................................................... 52
3.1.2 Internal data memory space.......................................................................................................... 53
3.1.3 Special function register (SFR) area ............................................................................................. 53