Altera DDR SDRAM Controller - Manual (Page 99)

© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide
C. HardCopy II Design Walkthrough
This walkthrough explains the additional steps that are needed to use the DDR or
DDR2 SDRAM Controller MegaCore function in a HardCopy II design.
f For details of a complete walkthrough, refer to “DDR & DDR2 SDRAM Controller
Walkthrough” on page 2–9 .
You can create a HardCopy II design either with the main target set to a HardCopy II
device and a Stratix II migration device, or with the main revision targeting a Stratix II
device and a companion revision targeting HardCopy II device.
To create a HardCopy II design, follow these steps:
1. Create a new Quartus II project and choose a family, a device, and a companion
device.
1 Altera recommends you choose a –4 speed grade device.
2. Launch IP Toolbench from the MegaWizard Plug-In Manager
3. Parameterize your custom variation.
4. Choose the constraints.
1 HardCopy II devices do not have dedicated hardware for DDR or DDR2
SDRAM capture on as many pins as the Stratix II companion, so there are
less DQS groups available.
5. Generate the variation.
6. Compile the design, which adds placement constraints for critical registers in the
read part of the datapath, and produces a report of the predicted timing margins.
7. The timing report that appears automatically is not available to the HardCopy
Design Centre, therefore add a set of timing constraints to help timing closure, by
running the DDR and DDR2 SDRAM timing wizard (DTW)—choose Tcl scripts
(Tools menu) and choose dtw.
f For more information on the HardCopy II design flow, refer to Back-End Design Flow
for HardCopy Series Device s chapter in volume 2 of the Hardcopy II Device Handbook.
8. To save time re-entering the parameters of the DDR or DDR2 SDRAM Controller
MegaCore function, import the parameters from the <variation
name>_ddr_setting.txt file, by clicking Import… on the third page of the wizard.
9. The DTW also needs an estimate of the t
CO
on the pins that drive the clock to the
DDR or DDR2 SDRAM. When the design has been compiled extract these
automatically in the relevant pane of the wizard.
10. Click Finish. The DTW adds timing constraints to the project, which are preserved
when migrating to HardCopy II devices.