Altera DDR SDRAM Controller - Manual (Page 24)

2–14 Chapter 2: Getting Started
MegaWizard Plug-In Manager Design Flow
DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation
25. IP Toolbench uses a prefix (for example, ddr_, or ddr2_) for the names of all
memory interface pins. Enter a prefix for all memory interface pins associated
with this custom variation.
26. If you want to access the manual timing settings, click the Manual Timing tab.
Otherwise, click Finish and proceed to “Constraints” on page 2–15 .
f For more information on the manual timing settings, refer to Appendix A,
Manual Timing Settings .
27. Choose Automatic, Always, or Never in the Reclock resynchronized data to the
positive edge list.
28. Turn on Manual resynchronization control, only if you want to override the
wizard-calculated values.
1 Under most circumstances, IP Toolbench calculates the correct
resynchronization settings for your custom variation.
f
For more information on resynchronization, refer to “Resynchronization”
on page A–4 .
29. Turn on Manual postamble control, only if you want to override the
wizard-calculated values.
1 Under most circumstances, IP Toolbench calculates the correct postamble
settings for your custom variation.
f
For more information on postamble, refer to “DQS Postamble” on
page A–10 .
30. Turn on your timing analysis options.
31. Click Finish.
Figure 2–1. System Naming
DDR SDRAM
Other Logic
PLL
DDR SDRAM
Interface
example_top
Example Top-Level Design
my_ddr_sdram
DDR SDRAM Controller
Data Path
auk_ddr_sdram
my_system
System