Altera DDR SDRAM Controller - Manual (Page 44)

3–8 Chapter 3: Functional Description
Device-Level Description
DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation
The control_doing_wr and control_wdata_valid signals are completely
identical outputs from the controller when it is in DDR2 SDRAM mode. If the
controller is issuing full size write bursts, the control_dqs_burst signal should be
issued for one clock cycle longer than control_doing_wr. If the controller is not
writing for the full length of the memory burst length, the control_dqs_burst
signal should be kept asserted so that the DQS toggles for the full length of the burst.
DQS Group Block Diagrams
Figure 3–4 on page 3–9 shows the Stratix II DQS group block diagram; Figure 3–5 on
page 3–10 shows the Stratix DQS group block diagram; Figure 3–6 on page 3–11
shows the Cyclone II DQS group block diagram; and Figure 3–7 on page 3–12 shows
the Cyclone DQS group block diagram.