Altera DDR SDRAM Controller - Manual (Page 18)

2–8 Chapter 2: Getting Started
MegaWizard Plug-In Manager Design Flow
DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation
c Turning off the Display entity name for node name setting prevents the
timing analysis script from completing successfully. To enable this setting,
open the Assignments menu and click Settings. On the Settings page, click
Compilation Process Settings,
and then click More Settings. In the Name
list, select Display entity name for node name and in the Setting list, select
On
.
The results show how much slack you have for each of the various timing
requirements—negative slack means that you are not meeting timing. The Message
window shows various timing margins for your design.
If the verify timing script reports that your design meets timing, you have
successfully generated and implemented your DDR or DDR2 SDRAM Controller.
If the timing does not reach your requirements, adjust the resynchronization and
postamble clock phases on the IP Toolbench Manual Timings tab (refer to
“Manual
Timing Settings” on page A–1 ).
f For more information on how to achieve timing, refer to Appendix B, DDR SDRAM
on the Nios Development Board, Cyclone II Edition .
To view the constraints in the Quartus II Assignment Editor, choose Assignment
Editor
(Assignments menu).
1
If you have “?” characters in the Quartus II Assignment Editor, the Quartus II
software cannot find the entity to which it is applying the constraints, probably
because of a hierarchy mismatch. Either edit the constraints script, or enter the correct
hierarchy path in the Hierarchy tab (refer to step
24 on page 2–13 ).
f For more information on constraints, refer to “Constraints” on page 3–18 .
Program a Device
After you have compiled the SOPC Builder design, you can perform gate-level
simulation (refer to
“Simulate the SOPC Builder Design” on page 2–6 ) or program
your targeted Altera device to verify the SOPC Builder design in hardware.
With Altera's free OpenCore Plus evaluation feature, you can evaluate the DDR or
DDR2 SDRAM controller MegaCore function before you purchase a license.
OpenCore Plus evaluation allows you to produce a time-limited programming file.
f For more information on OpenCore Plus hardware evaluation using the DDR or
DDR2 SDRAM controller MegaCore function, refer to
“OpenCore Plus Evaluation”
on page 1–6 , “OpenCore Plus Time-Out Behavior” on page 3–3 , and the AN 320:
OpenCore Plus Evaluation of Megafunctions .
MegaWizard Plug-In Manager Design Flow
MegaWizard Plug-In Manager design flow involves the following steps:
1. Create a custom variation of the DDR or DDR2 SDRAM controller MegaCore
function using IP Toolbench from the MegaWizard Plug-In Manager.