Altera DDR SDRAM Controller - Manual (Page 28)

2–18 Chapter 2: Getting Started
MegaWizard Plug-In Manager Design Flow
DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation
2. For VHDL, edit generic_ddr_sdram.vhd to instantiate your memory model (the
file already contains three example Micron memory model instantiations).
or
For Verilog HDL, edit the memory instantiations in the testbench to match your
memory model.
3. Start the ModelSim-Altera simulator.
4. Change your working directory to your IP Toolbench-generated file directory
<directory name>\testbench\modelsim.
5. Type the following command:
set memory_model
r
where <model_name> is the filename of the downloaded memory model.
6. To simulate with an IP functional simulation model simulation, type the following
command:
source _ddr_sdram_vsim.tcl
r
7. For a gate-level timing simulation (VHDL or Verilog HDL ModelSim output from
the Quartus II software), type the following commands:
set use_gate_model 1
r
source _ddr_sdram_vsim.tcl
r
Simulating With Other Simulators
The IP Toollbench-generated Tcl script is for the ModelSim simulator only. If you
prefer to use a different simulation tool, follow these instructions. You can also use
the generated script as a guide. You also need to download and compile an
appropriate memory model.
1 The following variables apply in this section:
■ <QUARTUS ROOTDIR> is the Quartus II installation directory
■ <simulator name> is the name of your simulation tool
■ <device name> is the Altera device family name
■ <project name> is the name of your Quartus II top-level entity or module.
■ <testbench name> is the name of your testbench entity or module
■ <MegaCore install directory> is the DDR and DDR2 SDRAM Controller
installation directory