Altera DDR SDRAM Controller - Manual (Page 29)

Chapter 2: Getting Started 2–19
MegaWizard Plug-In Manager Design Flow
© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide
VHDL IP Functional Simulations
For VHDL simulations with IP functional simulation models, follow these steps:
1. Create a directory in the <project directory>\testbench directory.
2. Launch your simulation tool inside this directory and create the following
libraries:
■ altera_mf
■ lpm
■ sgate
■ <device name>
■ altera
■ auk_ddr_user_lib
3. Compile the files in Table 2–2 into the appropriate library. The files are in VHDL93
format.
Table 2–2. Files to Compile—VHDL IP Functional Simulation Models
Library Filename
altera_mf <QUARTUS ROOTDIR>/eda/sim_lib/altera_mf_components.vhd
<QUARTUS ROOTDIR>/eda/sim_lib/altera_mf.vhd
lpm <QUARTUS ROOTDIR>/eda/sim_lib/220pack.vhd
<QUARTUS ROOTDIR>/eda/sim_lib/220model.vhd
sgate <QUARTUS ROOTDIR>/eda/sim_lib/sgate_pack.vhd
<QUARTUS ROOTDIR>/eda/sim_lib/sgate.vhd
<device name> <QUARTUS ROOTDIR>/eda/sim_lib/<device name>_atoms.vhd
<QUARTUS ROOTDIR>/eda/sim_lib/<device name>_components.vhd
altera <QUARTUS ROOTDIR>/libraries/vhdl/altera/altera_europa_support_lib.vhd
auk_ddr_user_lib <MegaCore install directory>/lib/auk_ddr_tb_functions.vhd
<project directory>/<variation name>_auk_ddr_dqs_group.vhd
<project directory>/<variation name>_auk_ddr_clk_gen.vhd
<project directory>/<variation name>_auk_ddr_datapath.vhd
<project directory>/<variation name>_auk_ddr_datapath_pack.vhd
<project directory>/.vho
<MegaCore install directory>/lib/example_lfsr8.vhd
<project directory>/<variation name>_example_driver.vhd
<project directory>/ddr_pll_<device name>.vhd
<project directory>/ddr_pll_fb_<device name>.vhd (1)
<project directory>/<variation name>_auk_ddr_dll.vhd (2)
<project directory>/<project name>.vhd
<project directory>/testbench/<testbench name>.vhd
Notes to Table 2–2 :
(1) Fed-back clock mode only.
(2) Stratix series only.