Altera DDR SDRAM Controller - Manual (Page 17)

Chapter 2: Getting Started 2–7
SOPC Builder Design Flow
© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide
Edit the PLL
The IP Toolbench-generated example design includes a PLL, which has an input to
output clock ratio of 1:1 and a clock frequency that you entered in IP Toolbench. In
addition, IP Toolbench correctly sets all the phase offsets of all the relevant clock
outputs for your design. You can edit the PLL input clock to make it conform to your
system requirements. If you re-run IP Toolbench, it does not overwrite this PLL, if
you turn off Automatically generate the PLL, so your edits are not lost.
1 If you turn on Use fed-back clock for resynchronization, IP Toolbench generates a
second PLL—the fed-back PLL. You need not edit the fed-back PLL.
f For more information on the PLL, refer to “PLL Configurations” on page 3–13 .
To edit the example PLL, follow these steps:
1. Choose MegaWizard Plug-In Manager (Tools menu).
2. Select Edit an existing custom megafunction variation and click Next.
3. In your Quartus II project directory, for VHDL choose ddr_pll_.vhd;
for Verilog HDL choose ddr_pll_.v.
4. Click Next.
5. Edit the PLL parameters in the ALTPLL MegaWizard Plug-In Manager.
f For more information on the ALTPLL megafunction, refer to the Quartus II Help or
click Documentation in the ALTPLL MegaWizard Plug-In Manager.
Compile & Perform Timing Analysis
Before the Quartus II software compiles the SOPC Builder design, it runs the IP
Toolbench-generated Tcl constraints script, auto_add_constraints.tcl.
The auto_add_constraints.tcl script calls the add_constraints_for_name>.tcl script for each variation in your design. The add_constraints_for_name>.tcl script checks for any previously added constraints specific to that variation,
removes them, and then adds constraints for that variation.
The constraints script analyzes and elaborates your design, to automatically extract
the hierarchy to your variation. To prevent the constraints script analyzing and
elaborating your design, turn on Enable hierarchy control in the wizard, and enter
the correct hierarchy path to your datapath (refer to step
24 on page 2–13 ).
When the constraints script runs, it creates another script,
remove_constraints_for_
.tcl, which can be used to remove the
constraints from your design.
1
Click Start Compilation (Processing menu), to run the add constraints scripts,
compile the design, and perform timing analysis.
When the compilation is complete, the Quartus II processing message tab displays the
post-compilation timing analysis results. The results are also written to the name>_post_summary.txt file in your project directory.