Altera DDR SDRAM Controller - Manual (Page 34)

2–24 Chapter 2: Getting Started
MegaWizard Plug-In Manager Design Flow
DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation
Once compilation is complete, the auto_verify_ddr_timing.tcl script automatically
calls the verify timing script for each instance of the controller in your design. The
post-compilation timing analysis results are displayed in the Quartus II processing
messages tab and are written to the _post_summary.txt file in your
project directory.
To prevent the verify timing script from running, turn off Automatically run verify
timing script
in the wizard. To manually prevent the script from running, open a
Quartus II Tcl Console window and enter the following command:
set_global_assignment -name POST_FLOW_SCRIPT_FILE -remove
The results show how much slack you have for each of the various timing
requirements—negative slack means that you are not meeting timing. The Message
window shows various timing margins for your design.
If the verify timing script reports that your design meets timing, you have
successfully generated and implemented your DDR or DDR2 SDRAM Controller.
If the timing does not reach your requirements, adjust the resynchronization and
postamble clock phases on the IP Toolbench Manual Timings tab (refer to
Appendix A, Manual Timing Settings ).
To view the constraints in the Quartus II Assignment Editor, click Assignment Editor
(Assignments menu).
1 If you have “?” characters in the Quartus II Assignment Editor, the
Quartus II software cannot find the entity to which it is applying the
constraints, probably because of a hierarchy mismatch. Either edit the
constraints script, or enter the correct hierarchy path in the Hierarchy tab
(refer to step
24 on page 2–13 ).
f
For more information on constraints, refer to “Constraints” on page 3–18 .
Program a Device
After you have compiled the example design, you can perform gate-level simulation
(refer to
“Simulate the Example Design” on page 2–17 ) or program your targeted
Altera device to verify the example design in hardware.
With Altera's free OpenCore Plus evaluation feature, you can evaluate the DDR or
DDR2 SDRAM controller MegaCore function before you purchase a license.
OpenCore Plus evaluation allows you to generate an IP functional simulation model,
and produce a time-limited programming file.
f For more information on OpenCore Plus hardware evaluation using the DDR or
DDR2 SDRAM controller MegaCore function, refer to
“OpenCore Plus Evaluation”
on page 1–6 , “OpenCore Plus Time-Out Behavior” on page 3–3 , and AN 320:
OpenCore Plus Evaluation of Megafunctions .
Implement Your Design
In the MegaWizard Plug-In flow, to implement your design based on the example
design, replace the example driver in the example design with your own logic.