Altera DDR SDRAM Controller - Manual (Page 62)

3–26 Chapter 3: Functional Description
Interfaces & Signals
DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation
2. An ELMR command is issued to enable the internal delay-locked loop (DLL) in the
memory devices. An ELMR command is an LMR command with the bank address
bits set to address the extended mode register.
3. An LMR command sets the operating parameters of the memory such as CAS
latency and burst length. This LMR command is also used to reset the internal
memory device DLL. The DDR SDRAM controller allows 200 clock cycles to
elapse after a DLL reset and before it issues the next command to the memory.
4. A further PCH command places all the banks in their idle state.
5. Two ARF commands must follow the PCH command.
6. The final LMR command programs the operating parameters without resetting the
DLL.
The DDR SDRAM controller asserts the local_init_done signal, which shows that
it has initialized the memory devices.
DDR2 SDRAM Initialization Timing
The DDR2 SDRAM controller initializes the memory devices by issuing the following
command sequence:
■ NOP (for 200 ms, programmable)
■ PCH
■ ELMR, register 2
■ ELMR, register 3
■ ELMR, register 1
■ LMR
■ PCH
■ ARF
■ ARF
■ LMR
■ ELMR, register 1
■ ELMR, register 1
Figure 3–18 on page 3–27 shows a typical DDR2 SDRAM initialization timing
sequence, which is described below. The length of time between the reset and the
clock enable signal going high should be 200 ms. This time can be reduced for
simulation testing by setting the start-up timer parameter in IP Toolbench.