Altera DDR SDRAM Controller - Manual (Page 85)

A–7
Resynchronization
© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide
Figure A–4 shows the resynchronization registers for Stratix II series (non-DQS
mode).
Figure A–3. Resynchronization Registers—Stratix Series, Non-DQS Mode
Notes to Figure A–3 :
(1) IP Toolbench automatically inserts the intermediate resynchronization registers, depending on your choice of resynchronization phase.
(2) IP Toolbench automatically inserts these registers if the design needs them.
clk PLL
Clocked by Capture Clock
DQ local_rdata
resynch_clk
Reclock resynchronized data
to rising edge registers
(see Note 2)
Intermediate resynchronization registers
(see Note 1)
Resynchronization registers
Capture registers
Clocked by Resynchronization Clock
Clocked by System Clock
capture_clk