Altera DDR SDRAM Controller - Manual (Page 51)

Chapter 3: Functional Description 3–15
Device-Level Description
© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide
Figure 3–10 shows the Cyclone II configuration for use with any PLL multiply or
divide ratios including a ratio of one.
Figure 3–11 on page 3–15 shows the Cyclone configuration.
Figure 3–9. Stratix PLL Configuration (Note 1)
Note to Figure 3–9 :
(1) In most cases, clk or write_clk are used as the resynchronization and postamble clocks, therefore you need not use a separate clock output
from the PLL.
Stratix De v ice
clk_to_sdram
clk_to_sdram_n
DDR SDRAM
Controller
Stratix DLL
dqs_ref_clk
altddio
altddio
altddio
Note 1
clock_source Enhanced PLL
clk
write_clk
resynch_clk or
capture_clk
postamble_clk
C0
C1
C2
C3
DDR SDRAM
Figure 3–10. Cyclone II PLL Configuration
Cyclone II De v ice
clock_source
clk_to_sdram
clk_to_sdram_n
DDR SDRAM
Controller
PLL clk
write_clk
resynch_clk
altddio
altddio
C0
C1
C2
DDR SDRAM
Figure 3–11. Cyclone PLL Configuration
Cyclone De v ice
clock_source
clk_to_sdram
clk_to_sdram_n
DDR SDRAM
Controller
PLL clk
write_clk
altddio
altddio
C0
C1 DDR SDRAM