Altera DDR SDRAM Controller - Manual (Page 101)

© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide
D. Maximizing Performance
To achieve maximum performance, your design should use the fedback clock DQS
mode. You should use this mode for 267-MHz designs. However, there is no
automatic setup of the fedback PLL, or the resyncronization and postamble clock
phases in fedback clock DQS mode. Use the steps in this appendix to achieve timing
closure.
As an example, this appendix demonstrates how to close timing on an Altera Stratix II
Memory Board 2 with a Stratix II –4 speed-grade device. This appendix follows the
“MegaWizard Plug-In Manager Design Flow” on page 2–8 , but indicates the
differences or additional steps.
f
For more information on the Stratix II Memory Board 2, contact your local Altera
representative.
Achieving 267 MHz on a –4 speed grade device is easier with a narrow interface,
because there is likely to be less skew across the byte groups. Achieving 267 MHz is
also easier on smaller devices than larger devices, because the clock network is faster
in small devices.
Device & Board Settings
To specify the correct device and board settings, follow these steps:
1. When you create a new Quartus II project, select an EP2S60F1020C4 Stratix II
device.
2. In the MegaWizard Plug-In Manager, expand the Interfaces > Memory
Controllers directory then click DDR2 SDRAM Controller .
3. In the IP Toolbench—Parameterize window:
a. On the Memory tab, in the Presets list, choose Infineon HYS72T64000GU-3.7.
b. On the Controller tab, turn on Use fedback clock and Enable DQS mode.
c. On the Board Timings tab, type the following board trace delays:
■ 1500 ps for FPGA clock output
■ 1500 ps for memory DQ/DQS outputs
■ 3000 ps for the fedback clock trace, nominal delay
1
Use measurement or simulation to derive precise values for your board.