Altera DDR SDRAM Controller - Manual (Page 11)

© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide
2. Getting Started
Design Flow
The Altera DDR and DDR2 SDRAM Controller Compiler and the Quartus II software
provide many options for creating custom, high-performance DDR and DDR2
SDRAM designs.
You can parameterize the DDR and DDR2 SDRAM Controller Compiler using either
one of the following flows:
■ SOPC Builder flow
■ MegaWizard TM Plug-In Manager flow
The SOPC Builder flow creates a simpler, automatically-integrated system; the
MegaWizard Plug-In flow requires more user-customization.
Table 2–1 summarizes the advantages offered by the different parameterization flows.
SOPC Builder Design Flow
The SOPC Builder design flow involves the following steps:
1. In SOPC Builder, use IP Toolbench to create a custom variation of the DDR or
DDR2 SDRAM controller MegaCore function and implement and generate the rest
of your SOPC Builder system.
2. Create your design, based on the DDR or DDR2 SDRAM example design.
3. Perform functional simulation with IP functional simulation models.
4. Use the Quartus II software to edit the PLL(s), add constraints, compile, and
perform post-compilation timing analysis.
5. If you have a suitable development board, you can generate an OpenCore Plus
time-limited programming file, which you can use to verify the operation of the
design in hardware.
Table 2–1. Advantages of the Parameterization Flows
SOPC Builder Flow MegaWizard Plug-In Manager Flow
■ Requires minimal DDR or DDR2 SDRAM
design expertise
■ Simple and flexible GUI to create complete
DDR or DDR2 SDRAM system within hours
■ Automatically-generated simulation
environment
■ Create custom components and integrate
them via the component wizard
■ All components are automatically
interconnected via the Avalon-MM interface
■ More control of the system feature set
■ Design directly from the DDR or DDR2
SDRAM interface to peripheral device(s)
■ Achieves higher-frequency operation