Altera DDR SDRAM Controller - Manual (Page 83)

A–5
Resynchronization
© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide
Resynchronization Registers
Figure A–1 shows the resynchronization registers.
Figure A–1. Resynchronization Registers
Notes to Figure A–1 :
(1) IP Toolbench automatically inserts the intermediate resynchronization registers, depending on your choice of resynchronization phase.
(2) IP Toolbench automatically inserts these registers if the design needs them.
clk PLL
DQS
Clocked by delayed DQS Clock
DQ local_rdata
resynch_clk
Reclock resynchronized data
to rising edge registers
(see Note 2)
90 o
Intermediate resynchronization registers
(see Note 1)
Resynchronization registers
Capture registers
Clocked by Resynchronization Clock
Clocked by System Clock