Altera DDR SDRAM Controller - Manual (Page 25)

Chapter 2: Getting Started 2–15
MegaWizard Plug-In Manager Design Flow
© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide
Constraints
To choose the constraints for your device, follow these steps:
1. Click Step 2: Constraints in IP Toolbench.
2. Choose the positions on the device for each of the DDR SDRAM byte groups. To
place a byte group, select the byte group in the drop-down box at your chosen
position.
1 The floorplan matches the orientation of the Quartus II floorplanner. The
layout represents the die as viewed from above. A byte group consists of
four or eight DQ pins, a DM pin, and a DQS pin.
1
IP Toolbench chooses the correct positions, if you are using an Altera board
preset.
Set Up Simulation
An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model
produced by the Quartus II software. The model allows for fast functional simulation
of IP using industry-standard VHDL and Verilog HDL simulators.
c You may only use these simulation model output files for simulation
purposes and expressly not for synthesis or any other purposes. Using these
models for synthesis will create a nonfunctional design.
To generate an IP functional simulation model for your MegaCore function, follow these steps:
1. Click Step 3: Set Up Simulation in IP Toolbench.
2. Turn on Generate Simulation Model.
3. Choose the language in the Language list.
1 To use the IP Toolbench-generated testbench, choose the same language
that you chose for your variation.
4. Some third-party synthesis tools can use a netlist that contains only the structure
of the MegaCore function, but not detailed logic, to optimize performance of the
design that contains the MegaCore function. If your synthesis tool supports this
feature, turn on Generate netlist.
5. Click OK.
Generate
To generate your MegaCore function, follow these steps:
1. Click Step 4: Generate in IP Toolbench.
Table 2–1 describes the generated files and other files that may be in your project
directory. The names and types of files specified in the IP Toolbench report vary
based on whether you created your design with VHDL or Verilog HDL.