Altera DDR SDRAM Controller - Manual (Page 71)

Chapter 3: Functional Description 3–35
Parameters
© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide
Table 3–15 shows the clocking options.
Table 3–15. Clocking Options
Parameter Description
Enable DQS mode When turned on, the registers that capture data from the DQ pins during
reads are clocked by a delayed version of DQS. Otherwise, a PLL-
generated clock captures the data (Stratix series only).
DQS mode provides higher performance than non-DQS mode. (refer to
AN 328: Interfacing DDR2 SDRAM with Stratix II Devices ).
Only top and bottom banks support DQS circuitry, but non-DQS mode
uses side banks too.
(1)
Use non-migratable DQ, DQS, and DM pins Only Stratix II devices support this option.
When the option is turned off, there are pins that are common across
the devices in the same family. For example, the pins that are available in
EP2S130F1020C3 is also available in EP2S90F1020C3. If you compile a
DDR or DDR2 SDRAM design to an EP2S130F1020C3 device, later you
can easily migrate it to an EP2S90F1020C3 device.
When turned on, the wizard allows much greater flexibility in the
placement of DQ, DQS, and DM pins, but you lose the ability to migrate
the design to a migration device.
Use fedback clock When turned on, the wizard uses the fedback clock for
resynchronization or capture. This clock eases resynchronization for the
read data for interface speeds > 200 MHz. When you use this clock, the
design uses an additional feedback PLL.
When you turn on both DQS mode and fedback clock mode, IP
Toolbench issues a warning Resynchronization and Postamble settings
must be chosen manually in the Manual Timings pane when using
DQS Fedback Clock mode. Manual control allows you flexibility to
adjust the phase of both the resynchronization clock and postamble
clock. If you do not turn on Manual control, the postamble clock and the
resynchronization clocks are derived from either the system clock or the
write clock.
For more information on fedback clock usage for improving the
performance, refer to
Appendix D, Maximizing Performance . (1)
Note to Table 3–15 :
(1) For block diagram of the registers, refer to Figure A–2 and Figure A–4 on page A–6 .