Altera DDR SDRAM Controller - Manual (Page 105)

© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide
Preliminary
Additional Information
Revision History
The following table shows the revision history for this user guide.
How to Contact Altera
For the most up-to-date information about Altera products, see the following table.
Typographic Conventions
The following table shows the typographic conventions that this document uses.
Date Version Changes Made
March 2009 9.0 Updated release information.
November 2008 8.1 Updated release information.
May 2008 8.0 Updated device support.
October 2007 7.2 ■ Updated walkthrough.
■ Added more information on resynch_clk_edge_select signal.
May 2007 7.1 Updated device support.
March 2007 7.0 No changes.
December 2006 6.1 Updated format.
June 2006 3.4.1 Improved definition of burst length.
April 2006 3.4.0 ■ Implemented minor format changes.
■ Added fedback clock mode appendix.
■ Added PLL output options to IP Toolbench.
■ Added more datapath signal behavior.
December 2005 3.3.1 No changes.
Contact (Note 1)
Contact
Method Address
Technical support Website www.altera.com/support
Technical training Website www.altera.com/training
Email [email protected]
Altera literature services Email [email protected]
Non-technical support (General) Email [email protected]
(Software Licensing) Email [email protected]
Note:
(1) You can also contact your local Altera sales office or sales representative.