Altera DDR SDRAM Controller - Manual (Page 100)

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DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation
1 Some of these constraints may conflict with constraints added by the
MegaCore function. These conflicts are detected, and you should click Yes,
to let the DTW override these conflicts.
The timing assignments that are set are visible in the assignments editor.
11. If you are using the PLL reset circuit included in the example design created for
you, add the following false path assignment to your top-level .sdc file:
set_false_path -from [get_registers soft_reset_reg2_n] -to *
12. Choose Start > Timing Analyzer (Processing menu) to run timing analysis on the
design. The results appear in the timing analyzer section of the compilation report.
13. Create a HardCopy II companion revision that targets the HardCopy device, using
the Quartus II revisions feature that allows multiple variations within one project.
f
For more information on revisions, refer to the Quartus II Help.
a. Choose HardCopy II Utilities > Create/Overwrite HardCopy II Companion
Revision (Project menu), to create another revision in your project, which
allows you to use one project to target both the Stratix II and HardCopy II
devices.
b. Choose Revisions (Project menu) and set the HardCopy II revision to be
current. You may now compile the design.