Altera DDR SDRAM Controller - Manual (Page 86)

A–8
Resynchronization
DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation
Figure A–4 shows the resynchronization registers for Stratix II devices with fed-back
capture (refer to Table 3–15 on page 3–35 ).
Figure A–4. Resynchronization Registers—Stratix II Devices with Fed-back Capture
Notes to Figure A–4 :
(1) IP Toolbench automatically inserts the intermediate resynchronization registers, depending on your choice of resynchronization phase.
(2) IP Toolbench automatically inserts these registers if the design needs them.
clk PLL
Clocked by Capture Clock
DQ local_rdata
resynch_clk
Reclock resynchronized data
to rising edge registers
(see Note 2)
Intermediate resynchronization registers
(see Note 1)
Resynchronization registers
Capture registers
Clocked by Resynchronization Clock
Clocked by System Clock
Fed-back PLL
(Optional)
capture_clk