Altera DDR SDRAM Controller - Manual (Page 81)

A–3
Parameters
© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide
Table A–3 shows the capture options (non-DQS mode only).
Postamble clock setting 0 (clk, rising edge),
90 (write_clk, falling
edge),
180 (clk, falling edge)
270 (write_clk, rising
edge), or
dedicated
Selects which clock to use for the postamble logic: the
system clock, the write clock (a 90
° advanced version of the
system clock), or a dedicated postamble clock. Also defines
which edge of the chosen clock to use for the postamble
logic. If you select falling edge, the data path automatically
inserts inverters on the clock inputs to the postamble control
registers.
Dedicated clock phase 0 to 359 Allows you to enter the phase of the dedicated postamble
clock that is used for timing analysis. IP Toolbench uses this
value to set up the PLL phase shift.
Number of DQS delay
matching buffers 0 to 8 Inserts the chosen number of delay buffers on the undelayed
DQS in Stratix devices. Insert delay buffers when you are
using low frequencies, to ensure that the capture registers
are not disabled too early.
Table A–2. Postamble Options (Part 2 of 2)
Parameter Range Description
Table A–3. Capture Options
Parameter Range Description
Manual capture control On or off Turn on to specify the details of the clock used for the
capture logic. Otherwise, the details are calculated
automatically based on system timing,
“DQS Postamble” on
page A–10 .
Capture setting 0 (clk, rising edge),
90 (write_clk, falling
edge),
180 (clk, falling edge)
270 (write_clk, rising
edge), or
dedicated
Selects which clock to use for the capture logic: the system
clock, the write clock (a 90
° advanced version of the system
clock), or a dedicated capture clock. Also defines which edge
of the chosen clock to use for the capture logic. If you select
falling edge, the data path automatically inserts inverters on
the clock inputs to the capture registers.
Dedicated clock phase 0 to 359 Allows you to enter the phase of the dedicated capture clock
that is used for timing analysis. IP Toolbench uses this value
to set up the PLL phase shift.