Kontron COMe Starterkit Eval T2 - Manual (Page 92)

COM Express Interfaces
2.11.1.1. Connector and Cable Considerations
When implementing LVDS signal pairs on a single-ended Carrier Board connector, the signals of
a pair should be arranged so that the positive and negative signals are side by side. The trace
lengths of the LVDS signal pairs between the COM Express Module and the connector on the
Carrier Board should be the same as possible. Additionally, one or more ground traces/pins
must be placed between the LVDS pairs.
Balanced cables (twisted pair) are usually better than unbalanced cables (ribbon cable) for noise
reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling
effects and also tend to pick up electromagnetic radiation as common-mode noise, which is
rejected by the receiver.
Twisted pair cables provide a low-cost solution with good balance and flexibility. They are
capable of medium to long runs depending upon the application skew budget. A variety of
shielding options are available.
Ribbon cables are a cost effective and easy solution. Even though they are not well suited for
high-speed differential signaling they do work fine for very short runs. Most cables will work
effectively for cable distances of <0.5m.
The cables and connectors that are to be utilized should have a differential impedance of 100Ω
±15%. They should not introduce major impedance discontinuities that cause signal reflections.
For more information about this subject, refer to the 'LVDS Owners Manual' available from Texas
Instruments (http://www.ti.com).
2.11.1.2. Display Timing Configuration
The graphic controller needs to be configured to match the timing parameters of the attached flat
panel display. To properly configure the controller, there needs to be some method to determine
the display parameters. Different Module vendors provide differing ways to access display timing
parameters. Some vendors store the data in non-volatile memory with the BIOS setup screen as
the method for entering the data, other vendors might use a Module or Carrier based EEPROM.
Some vendors might hard code the information into the BIOS, and other vendors might support
panel located timing via the signals LVDS_I2C_CK and LVDS_I2C_DAT with an EEPROM
strapped to 1010 000x. Regardless of the method used to store the panel timing parameters, the
video BIOS will need to have the ability to access and decode the parameters. Given the
number of variables it is recommended that Carrier designers contact Module suppliers to
determine the recommend method to store and retrieve the display timing parameters.
The Video Electronics Standards Association (VESA) recently released DisplayID, a second
generation display identification standard that can replace EDID and other proprietary methods
for storing flat panel timing data. DisplayID defines a data structure which contains information
such as display model, identification information, colorimetry, feature support, and supported
timings and formats. The DisplayID data allows the video controller to be configured for optimal
support for the attached display without user intervention. The basic data structure is a variable
length block up to 256 bytes with additional 256 byte extensions as required. The DisplayID data
is typically stored in a serial EPROM connected to the LVDS_I2C bus. The EPROM can reside
on the display or Carrier. DisplayID is not backwards compatible with EDID. Contact VESA
(www.vesa.org) for more information.
2.11.1.3. Backlight Control
Backlight inverters are either voltage, PWM or resistor controlled. The COM Express
specification provides two methods for controlling the brightness. One method is to use the
backlight control and enable signals from the CPU chipset. These signals are brought on COM
Express LVDS_BKLT_EN and LVDS_BKLT_CTRL. LVDS_BKLT_CTRL is a Pulse Width
Modulated (PWM) output that can be connected to display inverters that accept a PWM input.
The second method it to use the LVDS I2C bus to control an I2C DAC. The output of the DAC
can be used to support voltage controlled inverters. The DAC can be used driving the backlight
voltage control input pin of the inverter. The reference design shown in Figure 34 on page 97
below supports this. A header is used to allow the user to configure the type of backlight inverter
signal used. In the example a DAC from Maxim is used ( MAX5362 http://www.maxim-ic.com).
PICMG ® COM Express ® Carrier Board Design Guide Rev. 2.0 / December 6, 2013
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