Kontron COMe Starterkit Eval T2 - Manual (Page 47)

COM Express Interfaces
The TPS2231 includes a number of integrated pull-up resistors. Other solutions may require
external pull-ups not shown in this schematic example.
CLKREQ# is used for dynamic-clock management. When the signal is pulled low, the dynamic-
clock management feature is not supported.
The ExpressCard PCIe reset signal, PERST#, is driven by the TPS2231. PERST# is asserted if
the power rails are out of spec or if the COM Express ExpressCard reset, EXCD0_PERST#, is
asserted.
WAKE# is asserted by the Express Card to cause the COM Express Module to wake-up at COM
Express Module pin B66 WAKE0#. WAKE0# is pulled up on the Module to facilitate the “wire-
ORed” interconnect from other WAKE0# sources.
SMB_CK and SMB_DAT are sourced from COM Express Module pins B13 and B14 respectively.
The SMBUS supports client-alerting, wireless RF management, and sideband management.
Support for the SMBUS is optional on the Carrier Board and the Express Card.
2.3.6. PCI Express Routing Considerations
New Carrier designs should route the PCIe lanes with 85Ω (+/- 15%) differential impedance.
Previous designs that supported Gen1 and Gen2 signaling used 92Ω (+/- 10%) differential
impedance. Gen1 only designs used 100Ω (+/- 20%) differential impedance. Newer designs
should use 85Ω (+/- 15%) differential impedance to support Gen1, Gen2 and Gen3 signaling.
Route the traces as differential pairs, preferably referenced to a continuous GND plane with a
minimum of via transitions.
PCIe pairs need to be length-matched within a given pair (“intra-pair”), but the different pairs do
not need to be closely matched (“inter-pair”).
PCB design rules for these signals are summarized in Section 6. 'Carrier Board PCB Layout
Guidelines' on page 173.
2.3.6.1. Polarity Inversion
Per the PCI Express Card Electromechanical Specification, all PCIe devices must support
polarity inversion on each PCIe lane, independently of the other lanes. This means that, for
example, you can route the Module PCIE_TX0+ signal to the corresponding ‘-’ pin on the slot or
target device, and the PCIE_TX0- signal to the corresponding ‘+’ pin. If this makes the layout
cleaner, with fewer layer transitions and better differential pairs, then take advantage of this PCIe
feature.
2.3.6.2. Lane Reversal
PCIe lane reversal is not supported on the COM Express general purpose PCIe lanes. For x1
links, lane reversal is not relevant. It would potentially be useful for a x4 link, but is not supported
in the COM Express specification. It is also not supported by the current crop of South Bridge
chip-set components commonly used to create the general purpose PCIe lanes on COM Express
Modules.
Lane reversal is supported for the COM Express x16 PEG interface. See Section 2.4. 'PEG
(PCI Express Graphics)' on page 48 for details.
PICMG ® COM Express ® Carrier Board Design Guide Rev. 2.0 / December 6, 2013
47/218