Kontron COMe Starterkit Eval T2 - Manual (Page 37)

COM Express Interfaces
2.3.5.2. Reset
The PCI Interface of the COM Express Type 2 Module shares the reset signal 'PCI_RESET#'
with the PCI Express interface. PCI_RESET# is not available on all COM Express Module
Types. When design a carrier to support Module Types supporting PCI_RESET#, it is
recommended to use PCI_RESET# to generate PCIE_RESETn#. If the carrier supports COM
Express Module Types without PCI_RESET#, then it is recommended to use the COM Express
signal CB_RESET# as this signal is available on all COM Express pin-out types. The signal
PCIE_RESETn# in the schematics below is a buffered copy of either the PCI_RESET# or the
CB_RESET# signal. It is not the same signal as PCI_RESET#.
2.3.5.3. x1 Slot Example
An example of a x1 PCIe slot is shown in Figure 7 below. The source specification for slot
implementations is the PCI-SIG PCI Express Card Electromechanical Specification.
Figure 7: PCI Express x1 Slot Example
The example above shows COM Express PCIe lane 0 connected to the slot. Other lanes may be
used, depending on what is available on the particular Module being used.
No coupling caps are required on the PCIe data or clock lines. The PCIe TX series coupling
caps on the data lines are on the COM Express Module. The PCIe RX coupling caps are up on
the slot card.
Slot signals REFCLK+ and REFCLK- (pins A13 and A14) are driven by the Clock Buffer, which is
shown in Figure 6 'PCIe Reference Clock Buffer' on page 35. If there is only one PCIe target on
the Carrier Board, the Clock Buffer may be omitted and the slot REFCLK signals may be driven
directly by the COM Express Module.
The slot PERST# signal (pin A11) is driven by a buffered copy of the COM Express PCI_RESET#
signal. A buffered copy of CB_RESET# could also be used. If the Carrier Board only has one or
two target devices, an unbuffered PCI_RESET# or CB_RESET# could be used.
The slot signals PRSNT1# and PRSNT2# are part of a mechanism defined in the PCI Express
Card Electromechanical Specification to allow hot-plugged PCIe cards. However, most
systems do not implement the support circuits needed to complete hot-plug capability. If used,
the scheme works as follows: in Figure 7 above, PRSNT1# (pin A1) is pulled low on the Carrier
Board through R14. On the slot card, PRSNT1# is routed to PRSNT2# (pin B17). The state of
slot pin B17 may be read back by the BIOS or system software, if routed to an input port pin that
can be read by software. If a slot card is present, this pin reads back low; if the slot is empty, the
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PRSNT#1_SLOT0
PRSNT#2_SLOT0
VCC_3V3
VCC_3V3_SBY
VCC_12V
VCC_3V3
VCC_3V3
VCC_12V
PCIE_RESET1#
PCIE_CLK_REF0+
PCIE_CLK_REF0- CEX PCIE_TX0+
CEX PCIE_TX0-
SMB_CK_S0
SMB_DAT_S0
CEX WAKE0#
CEX PCIE_RX0-
CEX PCIE_RX0+
R14
0R
R15
4k7
TP1
Do Not Stuff
J1
XPCIEXPR1X
+12V
B1
+12V
B2
RSVD0
B3
GND
B4
SMCLK
B5
SMDAT
B6
GND
B7
+3.3V
B8
JTAG1
B9
3.3VAUX
B10
WAKE#
B11
RSVD1
B12
GND
B13
HSOp(0) B14
HSOn(0)
B15
GND
B16
PRSNT#2
B17
GND
B18
PRSNT#1
A1
+12V
A2
+12V
A3
GND
A4
JTAG2
A5
JTAG3 A6
JTAG4
A7
JTAG5
A8
+3.3V
A9
+3.3V
A10
PERST#
A11
GND
A12
REFCLK+
A13
REFCLK-
A14
GND
A15
HSIp(0)
A16
HSIn(0)
A17
GND
A18
X
2
X
1
X
1
X
2