Kontron CP383 User Manual
Cp383
Table of contents
Document Outline
- Revision History
- Imprint
- Copyright
- Table of Contents
- List of Tables
- 1-2 System Relevant Information 1 - 7
- 1-3 CP383 Main Specifications 1 - 10
- 1-4 CP383 Digital Input Specifications 1 - 11
- 1-5 CP383 Digital Output Specifications 1 - 11
- 1-6 Applied Standards 1 - 12
- 1-7 Related Publications 1 - 13
- 2-1 Pinout of the Digital Input and Output Interface Connector CON2 2 - 7
- 2-2 Pinout of the CPCI Connector CON1 (J1) 2 - 8
- 2-3 Digital Input Function Modes of the CP383 2 - 9
- 4-1 Backend Register Address Map 4 - 8
- 4-2 Input Data Register 4 - 9
- 4-3 Transparent Input Data Register 4 - 9
- 4-4 Input Control Register 4 - 10
- 4-5 Programmable Input Sample Rates 4 - 10
- 4-6 Input Event Mask Register 4 - 11
- 4-7 Input Event Polarity Register 4 - 11
- 4-8 Input Status Register 4 - 11
- 4-9 Input Latch-on-Event Register 4 - 12
- 4-10 Input Pattern Mask Register 4 - 12
- 4-11 Input Pattern Compare Register 4 - 12
- 4-12 Output Data Register 4 - 13
- 4-13 Output Control Register 4 - 13
- 4-14 Output Status Register 4 - 13
- 4-15 Hardware Debug Register 4 - 14
- 4-16 Hardware Status Register 4 - 14
- 4-17 General Interrupt Enable Register 4 - 15
- 4-18 General Interrupt Pending Register 4 - 15
- 4-19 Output Status Register 4 - 15
- 4-20 Input IRQ Register 4 - 15
- 4-21 ROM Command Register 4 - 16
- 4-22 ROM Control Register 4 - 16
- 4-23 Opcodes and Commands 4 - 17
- 4-24 ROM Status Register 4 - 17
- 4-25 ROM Data Register 4 - 17
- 5-1 Maximum Input Power Voltage Limits 5 - 3
- 5-2 DC Input Voltage Ranges 5 - 3
- 5-3 Input Voltage Characteristics 5 - 5
- 4-4 Power Consumption Table 5 - 6
- 5-1 Debouncing Periods 6 - 4
- List of Figures
- 1-1 CP383 System Level Interfacing Diagram 1 - 8
- 1-2 CP383 Front Panel 1 - 9
- 1-3 CP383 Board (Front View) 1 - 9
- 2-1 CP383 Board Level Interfacing 2 - 4
- 2-2 Pin Layout of the Digital Input and Output Interface Connector CON2 2 - 6
- 2-3 CPCI Connector CON1 (J1) 2 - 8
- 4-1 Voltage Ranges 4 - 3
- 4-2 Input Channel Schematic 4 - 4
- 4-3 Input Configuration (Example for Channel 0) 4 - 4
- 4-4 Configuration Diagram for All Input Channels 4 - 5
- 4-5 Digital Output Connection for One Cluster 4 - 6
- 4-6 Digital Output Circuit for One Channel 4 - 6
- 4-7 External Reset Connection for One Cluster 4 - 7
- 5-1 Start-Up Ramp of the CP3-SVE180 AC Power Supply 5 - 4
- Proprietary Note
- Trademarks
- Environmental Protection Statement
- Explanation of Symbols
- For Your Safety
- General Instructions on Usage
- Two Year Warranty
- 1. Introduction
- 2. Functional Description
- 3. Installation
- 4. Configuration
- 4.1 Jumper Settings
- 4.2 Digital Input Signal Requirements
- 4.3 Digital Output Signal Properties
- 4.4 Programming Interface
- 4.4.1 Access Control Logic (Address Decoder)
- 4.4.2 Reading Input Data
- 4.4.3 Debouncing Inputs
- 4.4.4 Detecting Input Events
- 4.4.5 Latching on Input Events
- 4.4.6 Comparing Input Patterns
- 4.4.7 Writing Output Data
- 4.4.8 Hardware Debug/Test Registers
- 4.4.9 Generating Interrupts
- 4.4.10 Programming the Board Capability ROM
- 5. Power Consumption