Kontron COMe Starterkit Eval T2 - Manual (Page 163)

Power and Reset
3.3. Design Considerations for Carrier Boards containing FPGAs/CPLDs
Very often, the Carrier Board will contain custom FPGA or other programmable devices which
require the loading of program code before they are usable. The Carrier Board designer needs
to take the necessary precautions to ensure that his Carrier Board logic is up and running before
the Module starts. Conflicts can occur if the Module is powered on and allowed to run before
devices on the Carrier Board are fully programmed and initialized. A typical example is an FPGA
which includes a PCIe device. Such devices must be initialized and ready before the chipset on
the Module performs link training and before the BIOS code performs enumeration of PCI
devices. The Module should therefore be prevented from starting before Carrier Board devices
are ready.
One method to achieve this is to delay assertion of the PWR_OK# signal to the Module until the
Carrier Board initialization process has completed. Note that during the phase when the Carrier
Board is powered and the Module is not powered there is potential for back drive voltages from
the carrier to the Module.
Another possibility is to use the SYS_RESET# signal to delay Module start-up. However,
depending on the Module implementation and the chipset used, SYS_RESET# may only be a
falling edge triggered signal and not a low active signal as was originally intended. In that case,
asserting SYS_RESET# may not hold the Module in the reset state. Also, PCIe link training will
occur regardless of the reset signal state for some chipsets.
Please refer to the COM.0 R2.1 specification (Power and System Management section) for more
details and check the Module provider’s documentation for their implementations of these
signals.
PICMG ® COM Express ® Carrier Board Design Guide Rev. 2.0 / December 6, 2013
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