Kontron COMe Starterkit Eval T2 - Manual (Page 34)

COM Express Interfaces
2.3.5. Schematic Examples
2.3.5.1. Reference Clock Buffer
The COM Express Specification calls for one copy of the PCIe reference clock pair to be brought
out of the Module. This clock is a 100MHz differential pair and is sometimes known as a “hint”
clock. The clock allows the PLL in the target PCIe device to lock faster onto the embedded clock
in the PCIe bit stream.
If the Carrier Board implements only one PCIe device or slot, then the PCIe reference clock pair
from the Module may be routed directly to that device or slot. However, if there are two or more
PCIe devices or slots on the Carrier Board, then the Module PCIe reference clock should be
buffered. A device which meets the jitter requirements for the intended PCI Express generation
must be used.
The IDT9DB233, IDT9DB433, IDT9DB844 have two, four and eight differential output replicas of
the input clock, respectively. Each target device (PCIe “device down” chip, slot, Express Card
slot, PEG slot) should get an individual copy of the reference clock. Similar parts may be
available from other vendors.
The PCIe Clock buffers have both PLL and bypass modes. In some situations it is preferable to
operate the clock buffer in bypass mode.
The reference clock pairs should be routed as directly as possible from source to destination.
PICMG ® COM Express ® Carrier Board Design Guide Rev. 2.0 / December 6, 2013
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