Kontron COMe Starterkit Eval T2 - Manual (Page 64)

COM Express Interfaces
PEG_RX1+ and PEG_RX1- are sourced from COM Express Module pins C55 and C56 and are
defined as SDVOB_INT+ and SDVOB_INT- in the COM Express Specification respectively.
They are driven by SDI+ and SDI- from the chip. The PEG Receive interface on the COM
Express Module is driven by the TX source (Interrupt) on the SDVO chip. The TX source needs
to be AC-coupled near the source (SDI pins).
EXT_RES is pulled low through a 1.0kΩ resistor to generate a reference-bias current.
PEG_TX0+/- through PEG_TX3- from COM Express Module pins are defined as SDVO_RED+/-,
GRN+/-, BLU+/- and CK+/- in the COM Express Specification respectively. They drive SDR+/-,
SDG+/-, SDB+/- and SDC+/- on the chip. The PEG Transmit interface on the COM Express
Module drives the RX load on the graphics chip.
SDVO_I2C_CLK and SDVO_I2C_DAT are sourced from COM Express Module pins D73 and
C73 respectively. A pull-up to 2.5V using a 3.5kΩ resistor is required for both lines on the Carrier
Board for a device-down application. For an SDVO slot design, pull-ups are on the SDVO plug-
in card.
The I2C Bus supports management functions and provides Manufacturer information, a model
number, and a part number.
RESET# is driven by the PCI_RESET1# from COM Express Module pin C23, PCI_RESET#,
after buffering. The signal resets the chip and causes initialization.
A1 establishes the I2C default address. Pulled Low = 0X70 (unconnected). Pulled High = 0X72
through a 4.7kΩ resistor.
HTPLUG – The Hot Plug input is driven by the Monitor Device, which causes the System OS to
initiate a Plug and Play sequence that results in identifying the configuration of the Monitor.
Protection diodes and a current-limiting resistor also are added.
TEST – The factory test pin needs to be tied low for normal operation.
EXT_SWING should be tied to AVCC pins through a 360Ω resistor. It sets the amplitude voltage
swing. Smaller values set a larger voltage swing and vice versa.
SDAROM and SCLROM interface to a non-volatile memory U17, Serial Prom AT24C04.
TX0+/- through TX2+/- DVI output pins are TMDS low voltage differential signals.
TXC+/- DVI Clock pins are TMDS low voltage differential signals.
SCLDDC and SDADDC should be pulled up with a 2.2kΩ resistor. They serve as the signals for
the I2C interface to the DVI connector. The interface supports the DDC (Display Data Channel)
standard for EDID (Extended Display Identification Data) over I2C. The EDID includes the
manufacturer’s name, product type, phosphor or filter type, timings supported by the display,
display size, luminance data and pixel mapping data (for digital displays only).
SDAROM and SCLROM external pull-ups are not required because they are internally pulled up.
They serve as signals for the I2C interface to EEPROM AT24C04.
The schematics also show the requirements for decoupling and the filter caps for the SIL1364
graphics chip.
Other SDVO Output Options: LVDS, NTSC
SDVO to LVDS interface chips are available from multiple vendors. One example is the Chrontel
CH7308.
SDVO to NTSC interface chips are available from multiple vendors including Chrontel.
Note: Please also follow the design guidelines from the SDVO chip vendor
2.5.2.3. Routing Considerations
For the SDVO interconnection between the COM Express Module and a third-party SDVO
compliant device, refer to Section 6.5.5. 'SDVO Trace Routing Guidelines' on page 185 below
and to the layout and routing considerations specified by the SDVO device manufacturer.
PICMG ® COM Express ® Carrier Board Design Guide Rev. 2.0 / December 6, 2013
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