Appendix b: sourcecode for port 80 decoder – Kontron COMe Starterkit Eval T2 User Manual
Page 209
Appendix B: Sourcecode for Port 80 Decoder
10.
Appendix B: Sourcecode for Port 80 Decoder
-- IO80 catcher for LPC bus.
-- File: LPC_IOW80_1.1.VHD
-- Revision: 1.1
-- Author: Eric Leonard (partially based on Nicolas Gonthier's T3001)
-- Subsequent modifications by:
--
Detlef Herbst and Travis Evans - 08/10/05
-- Decode only I/O writes to 80h
-- Features:
-- - I/O 80 access only (internally decoded)
-- - No support for read, only write.
-- - All signals synchronous to LPC clock
-- Notes:
-- - Unless otherwise noted, all signals are active high.
-- - Suffix "n" indicate active low logic.
--
-- - Successfully implemented on Brownsville baseboard with Seven Segment
-- - display P/N SA39-11 (common Anode - Low turns on segment) from Kingbright
-- Related documents:
--
- Low Pin Count (LPC) Interface Specification, Revision 1.0 (sept 1997)
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity LPC_IOW80 is port (
lclk:
in
std_logic;
-- LPC: 33MHz clock (rising edge)
lframe_n:
in
std_logic;
-- LPC: frame, active low
lreset_n:in
std_logic;
-- LPC: reset, active low
lad:
in
std_logic_vector(3 downto 0); -- LPC: multiplexed bus
seven_seg_L:
out
std_logic_vector(7 downto 0); -- SSeg Data output
seven_seg_H:
out
std_logic_vector(7 downto 0) -- SSeg Data output
);
end LPC_IOW80;
architecture RTL of LPC_IOW80 is
type LPC_State_Type is (
IDLE,
-- Waiting for a start condition
START,
-- Start condition detected
WADDN3,
-- I/O write address nibble 3 (A15..A12)
WADDN2,
-- I/O write address nibble 2 (A11..A8 )
WADDN1,
-- I/O write address nibble 1 (A7..A4)
WADDN0,
-- I/O write address nibble 0 (A3-A0)
WDATN1,
-- I/O write data nibble 0 (D7..D4)
WDATN0,
-- I/O write data nibble 1 (D3..D0)
WHTAR0,
-- I/O write host turn around phase 0
WHTAR1,
-- I/O write host turn around phase 1
WSYNC,
-- I/O write sync
WPTAR );
-- I/O write peripheral turn around
signal LPC_State: LPC_State_Type;
signal lframe_nreg: std_logic;
-- LPC frame register
signal lad_rin:
std_logic_vector(lad'range); -- LPC input registers
signal W_Data:
std_logic_vector(7 downto 0);
-- LPC input Post Code
begin
---------------------------------------------------------------------------
-- LPC bidirectional pins definition.
---------------------------------------------------------------------------
-- Input register to get some timing margin
P_input_register: process(lclk)
begin
if (lclk'event and lclk='1') then
lad_rin <= lad;
lframe_nreg <= lframe_n;
end if;
end process;
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