Rockwell Automation 1397 DC Drive Firmware 2.xx - Manual (Page 229)

Firmware Block Diagrams A–11
Publication 1397-5.0 — June, 2001
Figure A.11
Standard Outputs
* Default Selection
0
Analog Output 1
(+)CTB–24 (–)CTB–25
ANLG OUT
2 SRC
*n = 1
CUR LOOP ERR
TRIM OUTPUT
Analog (Metering) Outputs (n = 1, 2)
ANLG OUT 1
GAIN
100 ms
ARM VOLT
ZERO
From Field Control
Loop Block Diagram
4095
AVG
TIME
CUR LOOP REF
SPD LP FDBK
SPD LP REF
SPD LP ERROR
SPD LOOP OUT
SPD RAMP OUT
SPD RAMP IN
SPD SRC OUT
ATACH FDBK
FULL SCALE
POWER OUTPUT
SOFTWARE
SCALING
ANLG OUT
1 SRC
100 ms
AVG
TIME SOFTWARE
SCALING
D/A
D/A
Analog Output 2
(+)CTB–26 (–)CTB–25
ANLG OUT 1
ZERO
ANLG OUT 2
GAIN ANLG OUT 2
ZERO
OCL REF
OCL RAMP OUT
OCL FEEDBACK
OCL OUTPUT
*n = 2
FIELD REF
FIELD FDBK
From Outer Control
Loop Block Diagram
From Engineering Units
Outputs Block Diagram
From Speed Loop
Block Diagram
From Speed Ref
Ramp Block Diagram
From Speed Ref
Select Block Diagram
From Speed Loop
Block Diagram
From Current Minor
Loop Block Diagram
CUR LP FDBK
ENCODER FDBK