Rainbow Electronics DS31256 - Manual (Page 98)

DS31256
98 of 181
The host reads from the receive done queue to find which data buffers and their associated descriptors
are ready for processing.
The receive done queue is circular. A set of internal addresses within the device that are accessed by the
host and the DMA keep track of the queue’s addresses. On initialization, the host configures all of the
registers, as shown in
Table 9-F . After initialization, the DMA only writes to (changes) the write pointer
and the host only writes to the read pointer.
Empty Case
The receive done queue is considered empty when the read and write pointers are identical.
Receive Done-Queue Empty State
empty descriptor
empty descriptor
empty descriptor
read pointer > empty descriptor < write pointer
empty descriptor
empty descriptor
empty descriptor
Full Case
The receive done queue is considered full when the read pointer is ahead of the write pointer by one
descriptor. Therefore, one descriptor must always remain empty.
Receive Done-Queue Full State
valid descriptor
valid descriptor
empty descriptor < write pointer
read pointer > valid descriptor
valid descriptor
valid descriptor
valid descriptor
Table 9-F. Receive Done-Queue Internal Address Storage
REGISTER NAME ADDRESS
Receive Done-Queue Base Address 0 (lower word) RDQBA0 0730h
Receive Done-Queue Base Address 1 (upper word) RDQBA1 0734h
Receive Done-Queue DMA Write Pointer RDQWP 0740h
Receive Done-Queue Host Read Pointer RDQRP 073Ch
Receive Done-Queue End Address RDQEA 0738h
Receive Done-Queue FIFO Flush Timer RDQFFT 0744h
Note: Receive done-queue end address is not an absolute address. The absolute end address is “Base + RDQEA x 4.”