Rainbow Electronics DS31256 - Manual (Page 162)

DS31256
162 of 181
Figure 11-12. 8-Bit Write Cycle
Motorola Mode (LIM = 1)
Arbitration Disabled (LARBE = 0)
Bus Transaction Time = Timed from LRDY (LRDY = 0000)
LCLK
LA[19:0]
LD[7:0]
LD[15:8]
LR/ W
LDS
Address Valid
LBHE
LRDY
Three-State
Data Valid
1 2 3 4 5 6 7 8 9 10
Note: The LRDY signal must be detected by the 9th LCLK or the bus access attempted by the host is unsuccessful and the LBE status
bit is set.