Rainbow Electronics DS31256 User Manual
Page 124
DS31256
124 of 181
Register Name:
TDMAQ
Register Description: Transmit DMA Queues Control
Register Address:
0880h
Bit
#
7 6 5 4 3 2 1 0
Name n/a
n/a
n/a
n/a
TDQF TDQFE TPQF TPQFE
Default 0 0 0 0 0 0 0 0
Bit
#
15 14 13 12 11 10 9 8
Name n/a
n/a
n/a
n/a
n/a
TDQT2 TDQT1 TDQT0
Default 0 0 0 0 0 0 0 0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Transmit Pending-Queue FIFO Enable (TPQFE). See Section
for details.
Bit 1/Transmit Pending-Queue FIFO Flush (TPQLF). See Section
for details.
Bit 3/Transmit Done-Queue FIFO Enable (TDQFE). This bit must be set to 1 to enable the DMA to burst write
descriptors to the done queue. If this bit is set to 0, descriptors are written one at a time.
0 = done-queue burst write disabled
1 = done-queue burst write enabled
Bit 4/Transmit Done-Queue FIFO Flush (TDQF). When this bit is set to 1, the internal done-queue FIFO is
flushed by sending all data into the done queue. This bit must be set to 0 for proper operation.
0 = FIFO in normal operation
1 = FIFO is flushed
Bits 8 to 10/Transmit Done-Queue Status Bit Threshold Setting (TDQT0 to TDQT2). These bits determine
when the DMA sets the transmit DMA done-queue write (TDQW) status bit in the status register for DMA
(SDMA) register.
000 = set the TDQW status bit after each descriptor write to the done queue
001 = set the TDQW status bit after 2 or more descriptors are written to the done queue
010 = set the TDQW status bit after 4 or more descriptors are written to the done queue
011 = set the TDQW status bit after 8 or more descriptors are written to the done queue
100 = set the TDQW status bit after 16 or more descriptors are written to the done queue
101 = set the TDQW status bit after 32 or more descriptors are written to the done queue
110 = set the TDQW status bit after 64 or more descriptors are written to the done queue
111 = set the TDQW status bit after 128 or more descriptors are written to the done queue