Rainbow Electronics DS31256 - Manual (Page 2)

DS31256
2 of 181
TABLE OF CONTENTS
1. MAIN FEATURES........................................................................................................................ 6
2. DETAILED DESCRIPTION........................................................................................................ 7
3. SIGNAL DESCRIPTION ........................................................................................................... 13
3.1 O VERVIEW /S IGNAL L IST .............................................................................................................................. 13
3.2 S ERIAL P ORT I NTERFACE S IGNAL D ESCRIPTION ......................................................................................... 18
3.3 L OCAL B US S IGNAL D ESCRIPTION .............................................................................................................. 19
3.4 JTAG S IGNAL D ESCRIPTION ....................................................................................................................... 21
3.5 PCI B US S IGNAL D ESCRIPTION ................................................................................................................... 22
3.6 PCI E XTENSION S IGNALS ............................................................................................................................ 25
3.7 S UPPLY AND T EST S IGNAL D ESCRIPTION .................................................................................................... 25
4. MEMORY MAP .......................................................................................................................... 26
4.1 I NTRODUCTION ............................................................................................................................................ 26
4.2 G ENERAL C ONFIGURATION R EGISTERS (0 XX ) ............................................................................................ 26
4.3 R ECEIVE P ORT R EGISTERS (1 XX ) ................................................................................................................ 27
4.4 T RANSMIT P ORT R EGISTERS (2 XX ).............................................................................................................. 27
4.5 C HANNELIZED P ORT R EGISTERS (3 XX ) ....................................................................................................... 28
4.6 HDLC R EGISTERS (4 XX ) ............................................................................................................................. 29
4.7 BERT R EGISTERS (5 XX ).............................................................................................................................. 29
4.8 R ECEIVE DMA R EGISTERS (7 XX )................................................................................................................ 29
4.9 T RANSMIT DMA R EGISTERS (8 XX )............................................................................................................. 30
4.10 FIFO R EGISTERS (9 XX )....................................................................................................................... 30
4.11 PCI C ONFIGURATION R EGISTERS FOR F UNCTION 0 (PIDSEL/A XX ).................................................. 31
4.12 PCI C ONFIGURATION R EGISTERS FOR F UNCTION 1 (PIDSEL/B XX ).................................................. 31
5. GENERAL DEVICE CONFIGURATION AND STATUS/INTERRUPT ............................ 32
5.1 M ASTER R ESET AND ID R EGISTER D ESCRIPTION ....................................................................................... 32
5.2 M ASTER C ONFIGURATION R EGISTER D ESCRIPTION .................................................................................... 32
5.3 S TATUS AND I NTERRUPT ............................................................................................................................. 34
5.3.1 General Description of Operation ...................................................................................................... 34
5.3.2 Status and Interrupt Register Description .......................................................................................... 37
5.4 T EST R EGISTER D ESCRIPTION ..................................................................................................................... 43
6. LAYER 1 ...................................................................................................................................... 44
6.1 G ENERAL D ESCRIPTION ............................................................................................................................... 44
6.2 P ORT R EGISTER D ESCRIPTIONS ................................................................................................................... 48
6.3 L AYER 1 C ONFIGURATION R EGISTER D ESCRIPTION ................................................................................... 51
6.4 R ECEIVE V.54 D ETECTOR ............................................................................................................................ 56
6.5 BERT........................................................................................................................................................... 60
6.6 BERT R EGISTER D ESCRIPTION ................................................................................................................... 61
7. HDLC............................................................................................................................................ 67
7.1 G ENERAL D ESCRIPTION ............................................................................................................................... 67
7.2 HDLC R EGISTER D ESCRIPTION ................................................................................................................... 69
8. FIFO.............................................................................................................................................. 74
8.1 G ENERAL D ESCRIPTION AND E XAMPLE ...................................................................................................... 74
8.1.1 Receive High Watermark .................................................................................................................... 76
8.1.2 Transmit Low Watermark ................................................................................................................... 76
8.2 FIFO R EGISTER D ESCRIPTION ..................................................................................................................... 76
9. DMA.............................................................................................................................................. 83
9.1 I NTRODUCTION ............................................................................................................................................ 83
9.2 R ECEIVE S IDE .............................................................................................................................................. 85
9.2.1 Overview ............................................................................................................................................. 85
9.2.2 Packet Descriptors.............................................................................................................................. 90