Rainbow Electronics DS31256 User Manual
Page 101
DS31256
101 of 181
Register Name:
RDQFFT
Register Description: Receive Done-Queue FIFO Flush Timer
Register Address:
0744h
Bit
# 7 6 5 4 3 2 1 0
Name TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0
Default
0 0 0 0 0 0 0 0
Bit
# 15 14 13 12 11 10 9 8
Name TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8
Default
0 0 0 0 0 0 0 0
Note: Bits that are underlined are read-only, all other bits are read-write.
Bits 0 to 15/Receive Done-Queue FIFO Flush Timer Control Bits (TC0 to TC15). Please note that on system
reset, the timer is set to 0000h, which is defined as an illegal setting. If the receive done-queue FIFO is to be
activated (RDQFE = 1), then the host must first configure the timer to a proper state and then set the RDQFE bit to
one.
0000h = illegal setting
0001h = timer count resets to 1
FFFFh = timer count resets to 65,536
Register Name:
RDMAQ
Register Description: Receive DMA Queues Control
Register Address:
0780h
Bit
# 7 6 5 4 3 2 1 0
Name n/a
n/a
RDQF
RDQFE
RFQSF
RFQLF
n/a
RFQFE
Default 0 0 0 0 0 0 0 0
Bit
# 15 14 13 12 11 10 9 8
Name n/a
n/a
n/a
n/a
n/a
RDQT2 RDQT1 RDQT0
Default 0 0 0 0 0 0 0 0
Note: Bits that are underlined are read-only, all other bits are read-write.
Bit 0/Receive Free-Queue FIFO Enable (RFQFE). See Section
for details.
Bit
2/Receive Free-Queue Large Buffer FIFO Flush (RFQLF). See Section
for details.
Bit 3/Receive Free-Queue Small Buffer FIFO Flush (RFQSF). See Section
for details.
Bit 4/Receive Done-Queue FIFO Enable (RDQFE). To enable the DMA to burst write descriptors to the done
queue, this bit must be set to 1. If this bit is set to 0, messages are written one at a time.
0 = done-queue burst-write disabled
1 = done-queue burst-write enabled
Bit 5/Receive Done-Queue FIFO Flush (RDQF). When this bit is set to 1, the internal done-queue FIFO is
flushed by sending all data into the done queue. This bit must be set to 0 for proper operation.
0 = FIFO in normal operation
1 = FIFO is flushed