beautypg.com

Dma channel configuration ram, Figure 9-9. receive dma configuration ram, 5 dma channel configuration ram – Rainbow Electronics DS31256 User Manual

Page 102

background image

DS31256

102 of 181

Bits 8 to 10/Receive Done-Queue Status-Bit Threshold Setting (RDQT0 to RDQT2). These bits determine
when the DMA sets the receive DMA done-queue write (RDQW) status bit in the status register for DMA
(SDMA) register.

000 = set the RDQW status bit after each descriptor write to the done queue

001 = set the RDQW status bit after 2 or more descriptors are written to the done queue

010 = set the RDQW status bit after 4 or more descriptors are written to the done queue

011 = set the RDQW status bit after 8 or more descriptors are written to the done queue

100 = set the RDQW status bit after 16 or more descriptors are written to the done queue

101 = set the RDQW status bit after 32 or more descriptors are written to the done queue

110 = set the RDQW status bit after 64 or more descriptors are written to the done queue

111 = set the RDQW status bit after 128 or more descriptors are written to the done queue

9.2.5 DMA Channel Configuration RAM

There is a set of 768 dwords (3 dwords per channel times 256 channels) on-board the device that the host
uses to configure the DMA. It uses the DMA to store values locally when it is processing a packet. Most
of the fields within the DMA configuration RAM are for DMA use and the host never writes to these
fields. The host is only allowed to write (configure) to the lower word of dword 2 for each HDLC
channel. The host-configurable fields are denoted with a thick box as shown below.

Figure 9-9. Receive DMA Configuration RAM

msb

31

lsb
0

Receive DMA Configuration RAM

000h

004h

008h

HDLC
Channel 1

00Ch

010h

014h

HDLC
Channel 2

BF4h

BF8h

BFCh

HDLC
Channel 256

Fields shown within the thick box

are written by the Host; all other

fields are for usage by the DMA and

can only be read by the Host

Current Descriptor Pointer (16)

Start Descriptor Pointer (16)

Byte Count (13)

Threshold

Count (3)

Threshold(3

Unused (4)

CH
EN

Size
(2)

Current Descriptor Pointer (16)

Current Packet Data Buffer Address (32)

Start Descriptor Pointer (16)

Byte Count (13)

Threshold

Count (3)

Threshold(3)

Unused (4)

CH
EN

Size
(2)

Current Descriptor Pointer (16)

Start Descriptor Pointer (16)

Byte Count (13)

Threshold

Count (3)

Threshold(3

Unused (4)

CH
EN

Size
(2)

Current Packet Data Buffer Address (32)

Current Packet Data Buffer Address (32)

unused (5)

FBF

unused (5)

FBF

unused (5)

FBF