Rainbow Electronics DS31256 - Manual (Page 163)

DS31256
163 of 181
12. JTAG
12.1 JTAG Description
The DS31256 supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST.
Optional public instructions included are HIGHZ, CLAMP, and IDCODE.
Figure 12-1 is a block
diagram. The DS31256 contains the following items, which meet the requirements set by the IEEE
1149.1 Standard Test Access Port and Boundary Scan Architecture:
Test Access Port (TAP)
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
The TAP has the necessary interface pins JTCLK, JTRST, JTDI, JTDO, and JTMS. Details about these
pins can be found in Section
3.4 . Refer to IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-
1994 for details about the Boundary Scan Architecture and the TAP.
Figure 12-1. Block Diagram
BOUNDARY
SCAN REGISTER
IDENTIFICATION
REGISTER
BYPASS
REGISTER
INSTRUCTION
REGISTER
TEST ACCESS PORT
CONTROLLER
MU
X
SELECT
THREE-STATE
JTDI
10k
JTMS
10k
JTCLK JTRST
10k
JTDO