Rainbow Electronics DS31256 - Manual (Page 117)

DS31256
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The transmit DMA reads from the transmit pending-queue descriptor circular queue which data buffers
and their associated descriptors are ready for transmission. A set of internal addresses within the device
that are accessed by both the host and the DMA keep track of the circular queue addresses in the transmit
pending queue. On initialization, the host configures all of the registers shown in
Table 9-J . After
initialization, the DMA only writes to (changes) the read pointers and the host only writes to the write
pointers.
Empty Case
The transmit pending queue is considered empty when the read and write pointers are identical.
Transmit Pending-Queue Empty State
empty descriptor
empty descriptor
empty descriptor
read pointer > empty descriptor < write pointer
empty descriptor
empty descriptor
empty descriptor
Full Case
The transmit pending queue is considered full when the read pointer is ahead of the write pointer by one
descriptor. Therefore, one descriptor must always remain empty.
Transmit Pending-Queue Full State
valid descriptor
valid descriptor
empty descriptor < write pointer
read pointer > valid descriptor
valid descriptor
valid descriptor
valid descriptor
Table 9-J. Transmit Pending-Queue Internal Address Storage
REGISTER NAME ADDRESS
Transmit Pending-Queue Base Address 0 (lower word) TPQBA0 0800h
Transmit Pending-Queue Base Address 1 (upper word) TPQBA1 0804h
Transmit Pending-Queue Host Write Pointer TPQWP 080Ch
Transmit Pending-Queue DMA Read Pointer TPQRP 0810h
Transmit Pending-Queue End Address TPQEA 0808h
Note: Transmit free-queue end address is not an absolute address. The absolute end address is “Base + TPQEA.”